fix(apu): correct frame counter timing, add LP filter, mute aliased triangle
- Fix frame counter running at 2× speed: clock_frame_counter now skips odd CPU cycles (APU cycle = CPU/2), so envelope, sweep, and length counters tick at the correct rate. Fixes sweep-driven whistle in Megaman II. - Switch audio sampling to per-CPU-cycle granularity in run_until_frame_complete_with_audio to eliminate square-wave harmonic aliasing caused by sampling only once per instruction. - Add IIR one-pole low-pass filter (~14 kHz) to AudioMixer to smooth abrupt level transitions (crackling) introduced by correct envelope timing. - Mute triangle channel when timer_period < 2 (≥27 kHz), which aliases into the audible range at 48 kHz. Real NES RC circuit removes these ultrasonics; emulator must suppress them explicitly. - Update all APU bus tests to use correct (doubled) CPU cycle counts.
This commit is contained in:
@@ -331,9 +331,13 @@ impl Apu {
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};
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};
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let triangle = {
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let triangle = {
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// Timer period < 2 produces ultrasonic output (~28-56 kHz) that aliases
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// to audible frequencies when sampled at 48 kHz. Real hardware filters
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// this via the RC output stage; mute here to match that behaviour.
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let active = (self.channel_enable_mask & 0x04) != 0
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let active = (self.channel_enable_mask & 0x04) != 0
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&& self.length_counters[2] > 0
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&& self.length_counters[2] > 0
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&& self.triangle_linear_counter > 0;
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&& self.triangle_linear_counter > 0
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&& self.triangle_timer_period() >= 2;
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if active {
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if active {
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TRIANGLE_SEQUENCE[self.triangle_step as usize & 0x1F]
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TRIANGLE_SEQUENCE[self.triangle_step as usize & 0x1F]
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} else {
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} else {
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@@ -14,6 +14,9 @@ impl Apu {
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status
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status
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}
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}
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pub(crate) fn clock_frame_counter(&mut self) {
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pub(crate) fn clock_frame_counter(&mut self) {
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if self.cpu_cycle_parity {
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return;
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}
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let seq_len = if self.frame_mode_5step {
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let seq_len = if self.frame_mode_5step {
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APU_FRAME_SEQ_5_STEP_CYCLES
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APU_FRAME_SEQ_5_STEP_CYCLES
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} else {
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} else {
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@@ -5,7 +5,7 @@ fn apu_frame_irq_asserts_in_4_step_mode() {
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let mut bus = NativeBus::new(Box::new(StubMapper));
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let mut bus = NativeBus::new(Box::new(StubMapper));
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bus.write(0x4017, 0x00); // 4-step, IRQ enabled
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bus.write(0x4017, 0x00); // 4-step, IRQ enabled
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for _ in 0..14_918u32 {
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for _ in 0..29_832u32 {
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bus.clock_cpu(1);
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bus.clock_cpu(1);
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}
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}
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@@ -17,7 +17,7 @@ fn reading_4015_clears_apu_frame_irq_flag() {
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let mut bus = NativeBus::new(Box::new(StubMapper));
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let mut bus = NativeBus::new(Box::new(StubMapper));
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bus.write(0x4017, 0x00); // 4-step, IRQ enabled
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bus.write(0x4017, 0x00); // 4-step, IRQ enabled
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for _ in 0..14_918u32 {
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for _ in 0..29_832u32 {
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bus.clock_cpu(1);
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bus.clock_cpu(1);
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}
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}
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@@ -30,7 +30,7 @@ fn reading_4015_clears_apu_frame_irq_flag() {
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fn apu_frame_irq_inhibit_bit_disables_irq_and_clears_pending() {
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fn apu_frame_irq_inhibit_bit_disables_irq_and_clears_pending() {
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let mut bus = NativeBus::new(Box::new(StubMapper));
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let mut bus = NativeBus::new(Box::new(StubMapper));
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bus.write(0x4017, 0x00); // 4-step, IRQ enabled
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bus.write(0x4017, 0x00); // 4-step, IRQ enabled
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for _ in 0..14_918u32 {
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for _ in 0..29_832u32 {
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bus.clock_cpu(1);
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bus.clock_cpu(1);
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}
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}
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assert!(bus.poll_irq());
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assert!(bus.poll_irq());
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@@ -46,13 +46,13 @@ fn apu_frame_irq_inhibit_bit_disables_irq_and_clears_pending() {
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fn writing_4015_does_not_acknowledge_apu_frame_irq() {
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fn writing_4015_does_not_acknowledge_apu_frame_irq() {
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let mut bus = NativeBus::new(Box::new(StubMapper));
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let mut bus = NativeBus::new(Box::new(StubMapper));
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bus.write(0x4017, 0x00); // 4-step, IRQ enabled
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bus.write(0x4017, 0x00); // 4-step, IRQ enabled
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for _ in 0..14_918u32 {
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for _ in 0..29_832u32 {
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bus.clock_cpu(1);
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bus.clock_cpu(1);
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}
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}
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assert!(bus.poll_irq(), "frame IRQ must be pending");
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assert!(bus.poll_irq(), "frame IRQ must be pending");
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// Recreate pending frame IRQ and ensure $4015 write does not clear it.
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// Recreate pending frame IRQ and ensure $4015 write does not clear it.
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for _ in 0..14_918u32 {
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for _ in 0..29_832u32 {
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bus.clock_cpu(1);
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bus.clock_cpu(1);
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}
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}
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bus.write(0x4015, 0x00);
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bus.write(0x4015, 0x00);
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@@ -183,11 +183,11 @@ fn apu_length_counter_decrements_on_half_frame_when_not_halted() {
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bus.write(0x4003, 0x18); // length index 3 => value 2
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bus.write(0x4003, 0x18); // length index 3 => value 2
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assert_eq!(bus.apu.length_counters[0], 2);
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assert_eq!(bus.apu.length_counters[0], 2);
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for _ in 0..7_457u32 {
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for _ in 0..14_913u32 {
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bus.clock_cpu(1);
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bus.clock_cpu(1);
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}
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}
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assert_eq!(bus.apu.length_counters[0], 1);
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assert_eq!(bus.apu.length_counters[0], 1);
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for _ in 0..7_458u32 {
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for _ in 0..14_916u32 {
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bus.clock_cpu(1);
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bus.clock_cpu(1);
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}
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}
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assert_eq!(bus.apu.length_counters[0], 0);
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assert_eq!(bus.apu.length_counters[0], 0);
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@@ -218,13 +218,13 @@ fn quarter_frame_clocks_triangle_linear_counter() {
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bus.write(0x4008, 0x05); // control=0, reload value=5
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bus.write(0x4008, 0x05); // control=0, reload value=5
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bus.write(0x400B, 0x00); // set reload flag
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bus.write(0x400B, 0x00); // set reload flag
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for _ in 0..3_729u32 {
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for _ in 0..7_457u32 {
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bus.clock_cpu(1);
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bus.clock_cpu(1);
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}
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}
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assert_eq!(bus.apu.triangle_linear_counter, 5);
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assert_eq!(bus.apu.triangle_linear_counter, 5);
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assert!(!bus.apu.triangle_linear_reload_flag);
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assert!(!bus.apu.triangle_linear_reload_flag);
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for _ in 0..3_728u32 {
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for _ in 0..7_456u32 {
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bus.clock_cpu(1);
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bus.clock_cpu(1);
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}
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}
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assert_eq!(bus.apu.triangle_linear_counter, 4);
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assert_eq!(bus.apu.triangle_linear_counter, 4);
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@@ -238,7 +238,7 @@ fn quarter_frame_envelope_start_reloads_decay() {
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bus.write(0x4003, 0x00); // start envelope
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bus.write(0x4003, 0x00); // start envelope
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assert_ne!(bus.apu.envelope_start_flags & 0x01, 0);
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assert_ne!(bus.apu.envelope_start_flags & 0x01, 0);
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for _ in 0..3_729u32 {
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for _ in 0..7_457u32 {
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bus.clock_cpu(1);
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bus.clock_cpu(1);
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}
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}
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assert_eq!(bus.apu.envelope_decay[0], 15);
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assert_eq!(bus.apu.envelope_decay[0], 15);
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@@ -253,7 +253,7 @@ fn sweep_half_frame_updates_pulse_timer_period() {
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bus.write(0x4003, 0x02); // timer high => period 0x200
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bus.write(0x4003, 0x02); // timer high => period 0x200
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bus.write(0x4001, 0x82); // enable, period=1, negate=0, shift=2
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bus.write(0x4001, 0x82); // enable, period=1, negate=0, shift=2
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for _ in 0..7_457u32 {
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for _ in 0..14_913u32 {
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bus.clock_cpu(1);
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bus.clock_cpu(1);
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}
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}
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assert_eq!(bus.apu.read(0x4002), 0x80);
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assert_eq!(bus.apu.read(0x4002), 0x80);
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@@ -267,7 +267,7 @@ fn sweep_negative_pulse1_uses_ones_complement() {
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bus.write(0x4003, 0x02);
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bus.write(0x4003, 0x02);
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bus.write(0x4001, 0x8A); // enable, period=1, negate=1, shift=2
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bus.write(0x4001, 0x8A); // enable, period=1, negate=1, shift=2
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for _ in 0..7_457u32 {
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for _ in 0..14_913u32 {
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bus.clock_cpu(1);
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bus.clock_cpu(1);
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}
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}
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assert_eq!(bus.apu.read(0x4002), 0x7F);
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assert_eq!(bus.apu.read(0x4002), 0x7F);
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@@ -7,16 +7,23 @@ pub struct AudioMixer {
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samples_per_cpu_cycle: f64,
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samples_per_cpu_cycle: f64,
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sample_accumulator: f64,
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sample_accumulator: f64,
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last_output_sample: f32,
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last_output_sample: f32,
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// One-pole IIR low-pass filter state (approximates NES ~14 kHz RC filter).
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// Coefficient: a = exp(-2π * fc / fs). At fc=14000, fs=48000: a ≈ 0.160
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lp_coeff: f32,
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lp_state: f32,
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}
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}
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impl AudioMixer {
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impl AudioMixer {
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pub fn new(sample_rate: u32, mode: VideoMode) -> Self {
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pub fn new(sample_rate: u32, mode: VideoMode) -> Self {
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let cpu_hz = mode.cpu_hz();
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let cpu_hz = mode.cpu_hz();
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let lp_coeff = (-2.0 * std::f64::consts::PI * 14_000.0 / sample_rate as f64).exp() as f32;
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Self {
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Self {
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sample_rate,
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sample_rate,
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samples_per_cpu_cycle: sample_rate as f64 / cpu_hz,
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samples_per_cpu_cycle: sample_rate as f64 / cpu_hz,
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sample_accumulator: 0.0,
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sample_accumulator: 0.0,
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last_output_sample: 0.0,
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last_output_sample: 0.0,
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lp_coeff,
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lp_state: 0.0,
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}
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}
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}
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}
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@@ -27,6 +34,7 @@ impl AudioMixer {
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pub fn reset(&mut self) {
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pub fn reset(&mut self) {
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self.sample_accumulator = 0.0;
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self.sample_accumulator = 0.0;
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self.last_output_sample = 0.0;
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self.last_output_sample = 0.0;
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self.lp_state = 0.0;
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}
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}
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pub fn push_cycles(&mut self, cpu_cycles: u32, channels: ChannelOutputs, out: &mut Vec<f32>) {
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pub fn push_cycles(&mut self, cpu_cycles: u32, channels: ChannelOutputs, out: &mut Vec<f32>) {
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@@ -45,13 +53,20 @@ impl AudioMixer {
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}
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}
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let start = self.last_output_sample;
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let start = self.last_output_sample;
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let a = self.lp_coeff;
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let b = 1.0 - a;
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if samples == 1 {
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if samples == 1 {
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out.push(sample);
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let s = a * self.lp_state + b * sample;
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self.lp_state = s;
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out.push(s);
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} else {
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} else {
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let denom = samples as f32;
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let denom = samples as f32;
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for idx in 0..samples {
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for idx in 0..samples {
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let t = (idx + 1) as f32 / denom;
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let t = (idx + 1) as f32 / denom;
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out.push(start + (sample - start) * t);
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let interp = start + (sample - start) * t;
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let s = a * self.lp_state + b * interp;
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self.lp_state = s;
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out.push(s);
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}
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}
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}
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}
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self.last_output_sample = sample;
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self.last_output_sample = sample;
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@@ -108,8 +108,16 @@ impl NesRuntime {
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) -> Result<(), RuntimeError> {
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) -> Result<(), RuntimeError> {
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self.bus.begin_frame();
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self.bus.begin_frame();
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while !self.bus.take_frame_complete() {
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while !self.bus.take_frame_complete() {
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let cycles = self.step_instruction()?;
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self.bus.set_joypad_buttons(self.buttons);
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mixer.push_cycles(cycles, self.bus.apu_channel_outputs(), out_samples);
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let cpu_cycles = self.cpu.step(&mut self.bus).map_err(RuntimeError::Cpu)?;
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// Sample APU output once per CPU cycle for better audio resolution.
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// OAM DMA cycles (triggered inside cpu.step) are captured in the
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// first take_cpu_cycles_since_poll call of this instruction.
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for _ in 0..cpu_cycles {
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self.bus.clock_cpu(1);
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let actual = self.bus.take_cpu_cycles_since_poll();
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mixer.push_cycles(actual, self.bus.apu_channel_outputs(), out_samples);
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}
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}
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}
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self.frame_number = self.frame_number.saturating_add(1);
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self.frame_number = self.frame_number.saturating_add(1);
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Ok(())
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Ok(())
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