se.cherkasov
188444f987
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CI / rust (push) Has been cancelled
- Add ExRAM (modes 0-1) and fill-mode nametable routing via read_nametable_byte / write_nametable_byte mapper hooks - Separate sprite and BG CHR bank sets ($5120-$5127 vs $5128-$512B); BG banks are only active in 8x16 sprite mode - Use mapper.ppu_read_sprite() for sprite tile loads so they always use the sprite bank set regardless of PPU fetch phase - Replace CPU-cycle IRQ stub with scanline-based counter matching Mesen2 hardware behaviour: fire when counter == irq_scanline at dot 2 (start of scanline), irq_scanline=0 never fires - Add Mapper::notify_frame_start() called unconditionally at the PPU frame boundary; MMC5 uses it to hard-reset the scanline counter even when rendering is disabled (e.g. during room transitions), preventing stale counter values from shifting the CHR split by 8+ scanlines - Fix CHR bank calculation for modes 0-2: use << 3/2/1 shifts instead of & !7/3/1 masking to correctly convert bank numbers to 1KB indices - Correct $5204 read: bit 7 = IRQ pending (cleared on read), bit 6 = in-frame flag; IRQ line stays asserted until $5204 is read - Dispatch $4020-$5FFF CPU reads/writes to mapper cpu_read_low / cpu_write_low so MMC5 internal registers are accessible
270 lines
8.0 KiB
Rust
270 lines
8.0 KiB
Rust
use super::*;
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pub(crate) struct Tqrom119 {
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prg_rom: Vec<u8>,
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chr_rom: Vec<u8>,
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chr_ram: Vec<u8>,
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prg_ram: Vec<u8>,
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prg_ram_enabled: bool,
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prg_ram_write_protect: bool,
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mirroring: Mirroring,
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bank_regs: [u8; 8],
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bank_select: u8,
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irq_latch: u8,
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irq_counter: u8,
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irq_reload: bool,
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irq_enabled: bool,
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irq_pending: bool,
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}
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impl Tqrom119 {
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pub(crate) fn new(rom: InesRom) -> Self {
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Self {
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prg_rom: rom.prg_rom,
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chr_rom: rom.chr_data,
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chr_ram: vec![0; 0x2000],
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prg_ram: vec![0; 0x2000],
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prg_ram_enabled: true,
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prg_ram_write_protect: false,
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mirroring: rom.header.mirroring,
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bank_regs: [0; 8],
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bank_select: 0,
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irq_latch: 0,
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irq_counter: 0,
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irq_reload: false,
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irq_enabled: false,
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irq_pending: false,
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}
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}
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fn prg_bank_count_8k(&self) -> usize {
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(self.prg_rom.len() / 0x2000).max(1)
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}
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fn prg_mode(&self) -> bool {
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(self.bank_select & 0x40) != 0
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}
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fn chr_invert(&self) -> bool {
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(self.bank_select & 0x80) != 0
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}
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fn prg_bank_for_slot(&self, slot: usize) -> usize {
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let last = self.prg_bank_count_8k() - 1;
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let second_last = last.saturating_sub(1);
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match (self.prg_mode(), slot) {
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(false, 0) => self.bank_regs[6] as usize,
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(false, 1) => self.bank_regs[7] as usize,
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(false, 2) => second_last,
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(false, 3) => last,
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(true, 0) => second_last,
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(true, 1) => self.bank_regs[7] as usize,
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(true, 2) => self.bank_regs[6] as usize,
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(true, 3) => last,
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_ => 0,
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}
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}
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fn chr_bank_for_1k_page(&self, page: usize) -> u8 {
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let regs = &self.bank_regs;
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let mut layout = [0u8; 8];
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layout[0] = regs[0] & !1;
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layout[1] = layout[0].wrapping_add(1);
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layout[2] = regs[1] & !1;
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layout[3] = layout[2].wrapping_add(1);
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layout[4] = regs[2];
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layout[5] = regs[3];
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layout[6] = regs[4];
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layout[7] = regs[5];
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if self.chr_invert() {
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layout.rotate_left(4);
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}
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layout[page]
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}
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fn clock_irq_scanline(&mut self) {
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if self.irq_reload || self.irq_counter == 0 {
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self.irq_counter = self.irq_latch;
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self.irq_reload = false;
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} else {
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self.irq_counter = self.irq_counter.wrapping_sub(1);
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}
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if self.irq_enabled && self.irq_counter == 0 {
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self.irq_pending = true;
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}
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}
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fn chr_read_page(&self, bank: u8, offset: usize) -> u8 {
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if (bank & 0x40) != 0 {
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read_bank(&self.chr_ram, 0x0400, (bank & 0x07) as usize, offset)
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} else {
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read_bank(&self.chr_rom, 0x0400, (bank & 0x3F) as usize, offset)
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}
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}
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fn chr_write_page(&mut self, bank: u8, offset: usize, value: u8) {
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if (bank & 0x40) == 0 {
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return;
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}
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let page = (bank & 0x07) as usize;
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let idx = page * 0x0400 + (offset & 0x03FF);
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if let Some(cell) = self.chr_ram.get_mut(idx) {
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*cell = value;
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}
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}
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}
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impl Mapper for Tqrom119 {
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fn cpu_read(&self, addr: u16) -> u8 {
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if addr < 0x8000 {
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return 0;
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}
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let slot = ((addr - 0x8000) / 0x2000) as usize;
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let bank = self.prg_bank_for_slot(slot);
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read_bank(
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&self.prg_rom,
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0x2000,
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bank,
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((addr as usize) - 0x8000) & 0x1FFF,
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)
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}
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fn cpu_write(&mut self, addr: u16, value: u8) {
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match addr {
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0x8000..=0x9FFF if (addr & 1) == 0 => self.bank_select = value,
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0x8000..=0x9FFF => {
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let reg = (self.bank_select & 0x07) as usize;
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self.bank_regs[reg] = value;
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}
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0xA000..=0xBFFF if (addr & 1) == 0 => {
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self.mirroring = if (value & 1) == 0 {
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Mirroring::Vertical
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} else {
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Mirroring::Horizontal
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};
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}
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0xA000..=0xBFFF => {
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self.prg_ram_enabled = (value & 0x80) != 0;
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self.prg_ram_write_protect = (value & 0x40) != 0;
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}
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0xC000..=0xDFFF if (addr & 1) == 0 => self.irq_latch = value,
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0xC000..=0xDFFF => {
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self.irq_counter = 0;
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self.irq_reload = true;
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}
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0xE000..=0xFFFF if (addr & 1) == 0 => {
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self.irq_enabled = false;
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self.irq_pending = false;
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}
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0xE000..=0xFFFF => self.irq_enabled = true,
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_ => {}
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}
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}
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fn cpu_read_low(&mut self, addr: u16) -> Option<u8> {
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if (0x6000..=0x7FFF).contains(&addr) {
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if self.prg_ram_enabled {
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Some(self.prg_ram[(addr as usize) - 0x6000])
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} else {
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Some(0)
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}
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} else {
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None
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}
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}
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fn cpu_write_low(&mut self, addr: u16, value: u8) -> bool {
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if (0x6000..=0x7FFF).contains(&addr) {
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if self.prg_ram_enabled && !self.prg_ram_write_protect {
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self.prg_ram[(addr as usize) - 0x6000] = value;
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}
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true
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} else {
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false
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}
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}
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fn ppu_read(&self, addr: u16) -> u8 {
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if addr > 0x1FFF {
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return 0;
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}
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let page = (addr / 0x0400) as usize;
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let bank = self.chr_bank_for_1k_page(page);
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self.chr_read_page(bank, (addr as usize) & 0x03FF)
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}
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fn ppu_write(&mut self, addr: u16, value: u8) {
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if addr > 0x1FFF {
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return;
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}
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let page = (addr / 0x0400) as usize;
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let bank = self.chr_bank_for_1k_page(page);
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self.chr_write_page(bank, (addr as usize) & 0x03FF, value);
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}
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fn mirroring(&self) -> Mirroring {
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self.mirroring
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}
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fn clock_scanline(&mut self) {
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self.clock_irq_scanline();
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}
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fn needs_ppu_a12_clock(&self) -> bool {
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true
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}
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fn poll_irq(&mut self) -> bool {
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let out = self.irq_pending;
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self.irq_pending = false;
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out
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}
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fn save_state(&self, out: &mut Vec<u8>) {
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out.extend_from_slice(&self.bank_regs);
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out.push(self.bank_select);
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out.push(encode_mirroring(self.mirroring));
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out.push(self.irq_latch);
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out.push(self.irq_counter);
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out.push(u8::from(self.irq_reload));
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out.push(u8::from(self.irq_enabled));
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out.push(u8::from(self.irq_pending));
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out.push(u8::from(self.prg_ram_enabled));
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out.push(u8::from(self.prg_ram_write_protect));
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write_state_bytes(out, &self.prg_ram);
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write_state_bytes(out, &self.chr_ram);
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}
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fn load_state(&mut self, data: &[u8]) -> Result<(), String> {
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if data.len() < 17 {
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return Err("mapper state is truncated".to_string());
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}
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self.bank_regs.copy_from_slice(&data[0..8]);
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self.bank_select = data[8];
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self.mirroring = decode_mirroring(data[9]);
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self.irq_latch = data[10];
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self.irq_counter = data[11];
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self.irq_reload = data[12] != 0;
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self.irq_enabled = data[13] != 0;
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self.irq_pending = data[14] != 0;
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let mut cursor = 15usize;
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self.prg_ram_enabled = data[cursor] != 0;
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cursor += 1;
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self.prg_ram_write_protect = data[cursor] != 0;
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cursor += 1;
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let prg_ram = read_state_bytes(data, &mut cursor)?;
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if prg_ram.len() != self.prg_ram.len() {
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return Err("mapper state does not match loaded ROM".to_string());
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}
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self.prg_ram.copy_from_slice(prg_ram);
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let chr_ram = read_state_bytes(data, &mut cursor)?;
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if chr_ram.len() != self.chr_ram.len() || cursor != data.len() {
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return Err("mapper state does not match loaded ROM".to_string());
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}
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self.chr_ram.copy_from_slice(chr_ram);
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Ok(())
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}
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}
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